1. Field of Use
The present invention relate to synchronizing apparatus and more particularly to apparatus and methods for synchronizing asynchronously arranging bus signals with the operations of a synchronously operated processing unit.
2. Prior Art
A well known method of synchronization is to provide duplicated or cascaded bistable devices which are characterized by metastable operation for synchronizing asynchronous input signals with the operations of a processing unit prior to performing any operations on such asynchronous input signals. The term "metastable operation" refers to the prolonged transition time of a bistable device that may result if the input which causes the bistable device to change state is marginal in certain respects (e.g. width). The marginal input leaves the bistable device in a "metastable state" that is between the two stable states where it may remain for an indefinite time period before assuming one of the two strobe states. In synchronous systems, metastable operation is of great importance in that in such systems, the inputs to these systems must be synchronized to the clock units of such systems. If this is not done, then state register inputs may change during intervals when they should be constant. As a result, some state register flip-flops may respond to the old input value and others to the new input value.
Accordingly, the above duplication approach of using two cascaded flip-flops has been used to overcome this problem. That is, it is well known to lengthen the cascade of flip-flops which perform as input synchronizers. It is also possible to lengthening the clock pulse repetition time of the clock signals produced by a system's clock unit. However, the reliability is achieved at the expense of speed. It becomes particularly important to provide both reliable and high speed operation within processing units which operate in a pipelined mode of operation. In such units, the loss of a cycle can substantially reduce the performance of such units in that instruction execution is required to be completed within a cycle of operation.
Accordingly, it is a primary object of the present invention to provide an improved synchronization method and apparatus.
It is a further object of the present invention to provide an improved synchronization technique which minimizes the number of circuit elements to implement.